搜索资源列表
FPGADisplay
- 由ISE开发的FPGA工程文件,显示相关,包括视频接口,用Verilog开发,可以参考学习-ISE developed by the FPGA engineering documents, display related, including video interface, using Verilog development, you can refer to learning
OV7670_DDR2_VGA
- 在FPGA下的视频采集显示,采用纯Verilog编写,其中包括有OV7670摄像头,高速存储器DDR2,ADV芯片的VGA。-In FPGA video capture display, using pure Verilog prepared, which includes OV7670 camera, high-speed memory DDR2, ADV chip VGA.
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法,(Verilog HDL)设计所需的模块有: (1)带PLL的全局时钟管理模块 system_ctrl_pll.v (2)OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig (3)OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 (4)SDRAM数据交互控制器Sdram_Control_2Port (5)VGA时序
Nexys4FFTDemo-master
- A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output
bayer_to_vga
- Bayer 视频流转VGA的Verilog实现,经开发板测试可用(Bayer video streaming VGA Verilog implementation, the development board test available)
tnn7_code_201212141110
- 人脸检测与跟踪是一个重要而活跃的研究领域,它在视频监控、生物特征识别、视频编码等领域有着广泛的应用前景。该项目的目标是在FPGA板上实现实时系统来检测和跟踪人脸。人脸检测算法包括肤色分割和图像滤波。通过计算被检测区域的质心来确定人脸的位置。该算法的软件版本独立实现,并在matlab的静止图像上进行测试。虽然从MATLAB到Verilog的转换没有预期的那样顺利,实验结果证明了实时系统的准确性和有效性,甚至在不同的光线、面部姿态和肤色的条件下也是如此。所有硬件实现的计算都是以最小的计算量实时完成的
VGA
- vga code for fpga 3s500e spartan xilinx code verilog tutorial video graphics array in verilog interfacing with fpga xilins spattan 3e very easy to learn
VGA_to_DVI
- 采用Verilog语言将VGA视频信号转化成DVI视频信号,实现视频信号的转化(Using Verilog language to transform VGA video signal into DVI video signal and realize the transformation of video signal)
H.265视频压缩的FPGA实现
- 使用verilog语言实现H.265压缩算法,能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)